Input a logical equation and press enter to determine if both sides
are equivalent. Uses VHDL operators and syntax (case insensitive).
Also supports aliases for common operators, such as
'*' for 'and', '+' for 'or', '!' for 'not', and '^' for 'xor'.
These aliases do not need spaces around them.
Multiple statements can be equated on the same line
to check their total equivalency.

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