Yosys

Table Of Contents

Yosys Manual

Clifford Wolf

• Introduction
  • History of Yosys
  • Structure of this Document
• Basic Principles
  • Levels of Abstraction
    • System Level
    • High Level
    • Behavioural Level
    • Register-Transfer Level (RTL)
    • Logical Gate Level
    • Physical Gate Level
    • Switch Level
    • Yosys
  • Features of Synthesizable Verilog
    • Structural Verilog
    • Expressions in Verilog
    • Behavioural Modelling
    • Functions and Tasks
    • Conditionals, Loops and Generate-Statements
    • Arrays and Memories
  • Challenges in Digital Circuit Synthesis
    • Standards Compliance
    • Optimizations
    • Technology Mapping
  • Script-Based Synthesis Flows
  • Methods from Compiler Design
    • Lexing and Parsing
    • Multi-Pass Compilation
    • Static Single Assignment Form
• Approach
  • Data- and Control-Flow
  • Internal Formats in Yosys
  • Typical Use Case
• Implementation Overview
  • Simplified Data Flow
  • The RTL Intermediate Language
    • RTLIL Identifiers
    • RTLIL::Design and RTLIL::Module
    • RTLIL::Cell and RTLIL::Wire
    • RTLIL::SigSpec
    • RTLIL::Process
    • RTLIL::Memory
  • Command Interface and Synthesis Scripts
  • Source Tree and Build System
• Internal Cell Library
  • RTL Cells
    • Unary Operators
    • Binary Operators
    • Multiplexers
    • Registers
    • Memories
    • Finite State Machines
    • Specify rules
    • Formal verification cells
  • Gates
• Programming Yosys Extensions
  • Guidelines
  • The “stubsnets” Example Module
• The Verilog and AST Frontends
  • Transforming Verilog to AST
    • The Verilog Preprocessor
    • The Verilog Lexer
    • The Verilog Parser
  • Transforming AST to RTLIL
    • AST Simplification
    • Generating RTLIL
  • Synthesizing Verilog always Blocks
    • The ProcessGenerator Algorithm
      • Handling of Nonblocking Assignments
      • Handling of Blocking Assignments
      • Handling of Cases and if-Statements
      • Further Analysis of the Algorithm for Cases and if-Statements
    • The proc pass
  • Synthesizing Verilog Arrays
  • Synthesizing Parametric Designs
• Optimizations
  • Simple Optimizations
    • The opt_expr pass
    • The opt_muxtree pass
    • The opt_reduce pass
    • The opt_rmdff pass
    • The opt_clean pass
    • The opt_merge pass
  • FSM Extraction and Encoding
    • FSM Detection
    • FSM Extraction
    • FSM Optimization
    • FSM Recoding
  • Logic Optimization
• Technology Mapping
  • Cell Substitution
  • Subcircuit Substitution
  • Gate-Level Technology Mapping
• Evaluation, Conclusion, Future Work
  • Correctness of Synthesis Results
  • Quality of synthesis results
  • Conclusion and Future Work
• Auxiliary Libraries
  • SHA1
  • BigInt
  • SubCircuit
  • ezSAT
• Auxiliary Programs
  • yosys-config
  • yosys-filterlib
  • yosys-abc
• RTLIL Text Representation
  • Lexical elements
    • Characters
    • Identifiers
    • Values
    • Strings
    • Comments
  • File
    • Autoindex statements
    • Modules
    • Attribute statements
    • Signal specifications
    • Connections
    • Wires
    • Memories
    • Cells
    • Processes
    • Switches
    • Syncs
• Application Notes
• Evaluation of other OSS Verilog Synthesis Tools
  • Always blocks and blocking vs. nonblocking assignments
  • Arrays for memory modelling
  • For-loops and generate blocks
  • Extensibility
  • Summary and Outlook

Abstract

Most of today’s digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools.

In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL synthesis tool or add new features to an existing one. In these cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful.

In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was developed. This document covers the design and implementation of this tool. At the moment the main focus of Yosys lies on the high-level aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used by Yosys to perform advanced gate-level optimizations.

An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced by Yosys in this tests where successfully verified using formal verification and are comparable in quality to the results produced by a commercial synthesis tool.

This document was originally published as bachelor thesis at the Vienna University of Technology .

Abbreviations

AIG	And-Inverter-Graph
ASIC	Application-Specific Integrated Circuit
AST	Abstract Syntax Tree
BDD	Binary Decision Diagram
BLIF	Berkeley Logic Interchange Format
EDA	Electronic Design Automation
EDIF	Electronic Design Interchange Format
ER Diagram	Entity-Relationship Diagram
FOSS	Free and Open-Source Software
FPGA	Field-Programmable Gate Array
FSM	Finite-state machine
HDL	Hardware Description Language
LPM	Library of Parameterized Modules
RTLIL	RTL Intermediate Language
RTL	Register Transfer Level
SAT	Satisfiability Problem
VHDL	VHSIC Hardware Description Language
VHSIC	Very-High-Speed Integrated Circuit
YOSYS	Yosys Open SYnthesis Suite

Command Reference Manual

Table Of Contents

• Abstract
• Abbreviations
• Command Reference Manual

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Introduction