Improving netlistsvg
Michael Riegert29 Mar 2021
I had an idea after watching both BenEater's and 3Blue1Brown's videos on hamming codes: what if they were baked into the instruction set of a CPU? This would mean that each instruction in a program could be checked and corrected against single bit errors natively, and provide more reliable operation.
I spent a lot of time last summer messing around with VHDL and an Upduino. Nothing too serious, but it was a lot of fun. During one of the many nights I spent researching various things, I came across vpp. It was a preprocessor for VHDL that Takashige Sugie had been working on since 2007, licensed under GPL2.
While tools for generating block diagrams are already included in most HDL development environments, these are typically proprietary (though they may be free as in beer, they're not free as in freedom). Here is how to generate a block diagram from VHDL using netlistsvg (https://github.com/nturley/netlistsvg) and the open source FPGA toolchain on Linux.
It was on a car ride home from school in 5th grade that I asked my Dad what programming language I should learn, due mostly in part to jealousy about a kid my age who had gotten their own app into the iOS app store. I wanted to emulate their success. My Dad recommended Python, and later that week he bought me Beginning Game Development with Python and Pygame.
© 2021 Michael Riegert
Unless otherwise noted, content is under a CC BY 4.0 license.