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EccCPU - Error Correcting Code Central Processing Unit

Michael Riegert16 May 2021

I had an idea after watching both BenEater's and 3Blue1Brown's videos on hamming codes: what if they were baked into the instruction set of a CPU? This would mean that each instruction in a program could be checked and corrected against single bit errors natively, and provide more reliable operation.

Improving netlistsvg

Michael Riegert29 Mar 2021

Intel 4004 Assembler in Python

Michael Riegert12 Mar 2021

A photograph of a gold-legged intel 4004 processor, in an 8 wide DIP package

VHDL PreProcessor in Python

Michael Riegert12 Jan 2021

I spent a lot of time last summer messing around with VHDL and an Upduino. Nothing too serious, but it was a lot of fun. During one of the many nights I spent researching various things, I came across vpp. It was a preprocessor for VHDL that Takashige Sugie had been working on since 2007, licensed under GPL2.

VHDL block diagrams using netlistsvg

Michael Riegert30 Nov 2020

While tools for generating block diagrams are already included in most HDL development environments, these are typically proprietary (though they may be free as in beer, they're not free as in freedom). Here is how to generate a block diagram from VHDL using netlistsvg ( and the open source FPGA toolchain on Linux.

UnifiedNLP on LineageOS 16.0/17.1

Michael Riegert29 Oct 2020

A combination of the LineageOS and UnifiedNLP logos

VGA on the Upduino

Michael Riegert4 Sep 2020

The final assembly of the project, a VGA connector attached to the Upduino v3 FPGA

the second best time to plant a tree

Michael Riegert31 Aug 2020

It was on a car ride home from school in 5th grade that I asked my Dad what programming language I should learn, due mostly in part to jealousy about a kid my age who had gotten their own app into the iOS app store. I wanted to emulate their success. My Dad recommended Python, and later that week he bought me Beginning Game Development with Python and Pygame.

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