- Section 1.1
entity entity_name is generic (generic_list); port (port_list); end entity_name;
The port list must define the name, the mode (i.e. direction) and the type of each port on the entity:
entity HALFADD is port( A,B : in bit; SUM, CARRY : out bit ); end HALFADD; entity COUNTER is port ( CLK : in std_ulogic; RESET: in std_ulogic; Q : out integer range 0 to 15 ); end COUNTER;
The top-level entity in a simulatable VHDL model is usually “empty”, i.e. has no ports. Its architecture is usually the “test bench”:
entity TB_DISPLAY is end TB_DISPLAY; architecture TEST of TB_DISPLAY is -- component declaration(s) -- signal declarations begin -- component instance(s) -- test processes end TEST;
Each entity port acts like a signal which is visible in the architecture(s) of the entity. The mode (direction) of each port determines whether it may be read from or written to in the architecture:
|Mode||Read in Arch||Write in Arch|
If an entity has generics, these must be declared before the ports. They do not have a mode, as by definition they can only pass information into the entity:
entity AN2_GENERIC is generic ( DELAY: time := 1.0 ns ); port ( A,B : in std_ulogic; Z : out std_ulogic ); end AN2_GENERIC;
An entity may also contain declarations. Items declared are visible within the architecture(s) of the entity.
The keyword end may be followed by the keyword entity for clarity and consistency.
Entity declarations are supported for synthesis, providing the port types are acceptable to the logic synthesis tool. Usually, only generics of type integer are supported. Values for generics have to be supplied by the user at the time of synthesis.