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While and Infinite Loop

Used In

  • Process
  • Function
  • Procedure

Reference Manual

VHDL-93:
  • Section 8.8

Syntax

while condition loop
   -- sequential statements
end loop;
loop
    -- sequential statements
end loop;

Rules and Examples

The while loop repeats the enclosed sequence of statements while the condition is true. The condition is tested before each iteration:

process (A)
    variable I : integer range 0 to 4;
begin
    Z <= "0000";
    I := 0;
    while (I <= 3) loop
        if (A = I) then
            Z(I) <= '1';
        end if;
        I := I + 1;
    end loop;
end process;

While loops may be useful in test benches:

process
begin
    while NOW < MAX_SIM_TIME loop
        CLK <= not CLK ;
        wait for PERIOD/2;
    end loop;
    wait;
end process;

To prevent simulation hang-up, an infinite loop should usually contain at least one wait or exit statement:

process (A)
    variable I : integer range 0 to 4;
begin
    Z <= "0000";
    I := 0;    
    L1: loop
        exit L1 when I = 4;
        if (A = I) then
            Z(I) <= '1';
        end if;
        I := I + 1;
    end loop;    
end process;

Synthesis Issues

While and infinite loops are supported by some logic synthesis tools, with certain restrictions.

See Also