# Logical Operations

## Used In

- Expression

## Reference Manual

VHDL-93:- Section 7.2

## Syntax

See reference manual.

## Rules and Examples

The **logical operators** are predefined for **bit**, **boolean**, **bit_vector**, linear arrays of **boolean**, **std_logic** and **std_logic_vector** types. They return a value of the same type:

```
C <= A and B;
C <= A or B;
C <= A nand B;
C <= A nor B;
C <= A xor B;
C <= A xnor B;
C <= not B;
```

A | B | and | or | nand | nor | xor | xnor |
---|---|---|---|---|---|---|---|

0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |

0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |

1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |

1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |

The equality and inequality operators are predefined for all types, and they return a boolean value:

```
if (A = B) then -- equal to
-- other code here
end if;
if (A /= B) then -- not equal to
-- other code here
end if;
```

The other relational operators are predefined for all scalar types, and all one-dimensional array types. They also return a boolean value:

```
< -- less than
> -- greater than
<= -- less than or equal to
>= -- greater than or equal to
```

For arrays of different lengths, the predefined relational operators align the left-hand elements and compare corresponding positions. This can lead to unexpected results:

```
constant ARR1 : bit_vector := "0011";
constant ARR2 : bit_vector := "01";
-- (ARR1 < ARR2) will return true
```

The **&** operator is used to concatenate (join) arrays, or join new elements to an array:

```
Z_BUS(1 downto 0) <= '0' & B_BIT;
BYTE <= A_BUS & B_BUS;
```

For physical types (i.e. time), assignments must be dimensionally consistent:

```
variable TIME1,TIME2: time;
...
TIME1 := TIME2 * 2.5;
TIME1 := TIME2 / 4;
TIME1 := 3.6 ns + TIME2;
TIME1 := TIME2 * 6.67 ns; --illegal
```

Other numeric operators are exponentiation (******), absolute value (**abs**), modulus (**mod**), and remainder (**rem**).

Shift and rotate operators are defined for one-dimensional arrays of bit or boolean:

```
sll -- shift left logical
srl -- shift right logical
sla -- shift left arithmetic
sra -- shift right arithmetic
rol -- rotate left
ror -- rotate right
```

## Synthesis Issues

Most predefined operators are synthesizable, providing they are used with types accepted by the synthesis tool. See also type declarations and overloading.

The following are not usually synthesizable, except as part of a constant expression: exponentiation (**), division by other than 2, mod, rem.